Reconfigurabile Computing Systems (RCS)

English track of "Sisteme Reconfigurabile de Calcul"
IVF  ETTI

2017-2018

COURSE:  Monday,  room B124 15:20 - 17
RESOURCES:
  lecture notes and resources  (password will be announced in the )
Instructors: Radu DOGARU and Ioana DOGARU  

APPLICATIONS (LAB) Monday 9-13 in even-type weeks
Formerly the lab was organized in 4 hour sessions (3 major lab works L1,L2, L3 they are still preserved in the references).
Starting with this year the major labs will be divided into 2 units each (a total of 6 units) to
conform with the new directives (no more than 2 hours per lab session.)
A lab session is without break, 11-12:20 plus 10' for a written test quiz (the final mark for the lab consists in adding marks from 6 written tests) 
It is highly recommended to have a look on the Lab material before attending the session.
Room (lab.) , Instructor: Ioana DOGARU
                                        
Last weeks (13-14) may be used for people who did not attend (but only for good and provable reasons) one of the labs.
Graduation condition: At least 20 points (of all 40) in the lab (so, attending at least 3-4 labs with good results in the written test at the end of lab.)

contact:  radu_d@ieee.org  natural computing lab


EVALUATION:

Lab: 40 points (6 points max. for the test after each lab).
Course: 60 points (in 2 or 3 small exams (verificare) as programmed by the department - will be announced)

References (Romanian)
[1] I. Dogaru, R. Dogaru - Sisteme Reconfigurabile de Calcul
- Lucrari Practice, Editura Printech 2009
more details and English language references in the resources page




OBJECTIVES:

-    course 
Rapid prototyping is a key issue of actual developments on the IT market. Reconfigurable computing architectures, emerged on the market as very convenient compromise to remove long prototyping times in traditional hardware (VLSI) design and to offer a better flexibility in hardware than is usually achieved in traditional programmable systems (e.g.  microcontrollers).
The aim of this course is to systematically present the most actual reconfigurable architectures (e.g. FPGAs CPLDs, FPAAs), their associated design tools as well as a design guide for the steps required to obtain a finite product using the reconfigurable technology.
During the course some specific applications (called next “case applications”) will be considered such that any new concept introduced during the course will be grounded and motivated by its necessity for the “case application”. 

-    applications 
During the application sessions the most important aspects of designing with reconfigurable architectures will be introduced using development platforms from XESS (built around FPGAs from the Spartan II family) and software development tools such as Xilinx ISE. The last laboratory works consists on a full development cycle for the case applications, until the testing phase of the final product. 



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